/*
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * This file contains the configuration parameters for the ls1b_core board.
 */

#ifndef __CONFIG_LS1B_CORE_H
#define __CONFIG_LS1B_CORE_H

#include <asm/sizes.h>

#define CONFIG_MIPS32		1
#define CONFIG_CPU_LOONGSON1
#define CONFIG_CPU_LOONGSON1B
#define LS1BSOC 1

#define LS1X_SPI_SFC_PARAM	0x17	/* 设置SPI flash控制器的模式，加快启动
									div 2, double I/O + burst_en + memory_en 模式
									部分SPI flash可能不支持 导致启动不了 根据使用的spi flash型号修改 */

#define OSC_CLK		25000000 /* Hz */
#if 0
#define PLL_FREQ		0x1a
#define CPU_DIV		0x2
#define DDR_DIV		0x3
#else
#define PLL_FREQ		0x2a
#define CPU_DIV		0x3
#define DDR_DIV		0x5
#endif
#define PLL_DIV		(0x92082a00 | (CPU_DIV<<20) | (DDR_DIV<<14)) /* ((1<<31)|(4<<26)|(1<<25)|(1<<19)|0x2a00) */
#define PLL_CLK		((12+(PLL_FREQ&0x3f))*OSC_CLK/2 + ((PLL_FREQ>>8)&0x3ff)*OSC_CLK/2/1024)

#ifndef CPU_CLOCK_RATE
#define CPU_CLOCK_RATE	(PLL_CLK / ((PLL_DIV & DIV_CPU) >> DIV_CPU_SHIFT))	/* MHz clock for the MIPS core */
#endif
#define CPU_TCLOCK_RATE CPU_CLOCK_RATE
#define CONFIG_SYS_MIPS_TIMER_FREQ	(CPU_TCLOCK_RATE / 2)
#define CONFIG_SYS_HZ			1000

/* Cache Configuration */
#define CONFIG_SYS_DCACHE_SIZE		(8*1024)
#define CONFIG_SYS_ICACHE_SIZE		(8*1024)
#define CONFIG_SYS_CACHELINE_SIZE	32

/* Miscellaneous configurable options */
#define CONFIG_SYS_MAXARGS 16	/* max number of command args */
#define CONFIG_SYS_LONGHELP	/* undef to save memory */
#define CONFIG_SYS_PROMPT "=> "
#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)	/* Print Buffer Size */

#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE

#define CONFIG_SYS_MALLOC_LEN		(16 * 1024 * 1024)
#define CONFIG_SYS_BOOTPARAMS_LEN	(128 * 1024)

/* memory */
#define CONFIG_SYS_SDRAM_BASE		0x80000000	/* Cached addr */
#define CONFIG_SYS_INIT_SP_OFFSET	0x00040000
#define CONFIG_SYS_LOAD_ADDR		0x82000000
#define CONFIG_SYS_MEMTEST_START	0x80100000
#define CONFIG_SYS_MEMTEST_END		0x80800000
//#define CONFIG_DDR_CL3
#define CONFIG_DDR_CL5
//#define CONFIG_DDR16BIT 1
//#define EIGHT_BANK_MODE 1
#define CONFIG_MEM_SIZE 0x10000000

#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT

/* misc settings */
#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f() */
#define CONFIG_MISC_INIT_R

/* GPIO */
#define CONFIG_LS1X_GPIO

/* SPI Settings */
#define CONFIG_LS1X_SPI
#define CONFIG_SPI_CS
//#define CONFIG_SPI_CS_USED_GPIO
#define CONFIG_SF_DEFAULT_CS 0
#define CONFIG_SF_DEFAULT_SPEED	30000000
#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_WINBOND
#define CONFIG_SPI_FLASH_GIGADEVICE
#define CONFIG_SPI_FLASH_SST
#define CONFIG_CMD_SF
#define CONFIG_CMD_SPI

/* Flash Settings */
#define CONFIG_SYS_NO_FLASH	1

/* Env Storage Settings */
#if 1
/*
#define CONFIG_ENV_IS_IN_NVRAM	1
#define CONFIG_ENV_ADDR		0xBFC40000
#define CONFIG_ENV_SIZE		0x2000
*/
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SPI_CS	0
#define CONFIG_ENV_SPI_MAX_HZ	30000000
#define CONFIG_ENV_OFFSET	0x7e000
#define CONFIG_ENV_SIZE		0x2000	/* 8KB */
#define CONFIG_ENV_SECT_SIZE	256
#else
#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_OFFSET	0x40000
#define CONFIG_ENV_SIZE		0x2000
#endif

/* RTC configuration */
//#define CONFIG_RTC_LS1X
#define CONFIG_RTC_TOY_LS1X
#define CONFIG_CMD_DATE

/* NAND settings */
#define CONFIG_SYS_NAND_SELF_INIT
#define CONFIG_SYS_MAX_NAND_DEVICE	1
#define CONFIG_SYS_NAND_BASE	LS1X_NAND_BASE
#define CONFIG_NAND_LS1X
#define CONFIG_NAND_LS1X_MAX_CHIPS 1
#define CONFIG_CMD_NAND
#define CONFIG_MTD_DEBUG
#define CONFIG_MTD_DEBUG_VERBOSE	1
/* support for yaffs */
#define CONFIG_CMD_NAND_YAFFS

#define CONFIG_MTD_DEVICE	/* needed for mtdparts commands */
#define CONFIG_MTD_PARTITIONS	/* needed for UBI */
#define CONFIG_CMD_MTDPARTS

/* OHCI USB */
#define CONFIG_CMD_USB
#ifdef CONFIG_CMD_USB
#define CONFIG_USB_OHCI
#define CONFIG_USB_OHCI_LS1X
//#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS
//#define CONFIG_SYS_OHCI_USE_NPS		/* force NoPowerSwitching mode */
//#define CONFIG_SYS_USB_OHCI_CPU_INIT
#define CONFIG_SYS_USB_OHCI_BOARD_INIT
#define CONFIG_USB_HUB_MIN_POWER_ON_DELAY	500
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	1
#define CONFIG_SYS_USB_OHCI_REGS_BASE		0xbfe08000
#define CONFIG_SYS_USB_OHCI_SLOT_NAME		"ls1x-ohci"
#define CONFIG_USB_STORAGE
#endif

/* File System Support */
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
#define CONFIG_DOS_PARTITION
#define CONFIG_SUPPORT_VFAT
#define CONFIG_FAT_WRITE
//#define CONFIG_CMD_UBIFS	//uboot会增加100KB多的大小
#if defined(CONFIG_CMD_UBIFS)
#define CONFIG_CMD_UBI
#define CONFIG_RBTREE
#endif
#define CONFIG_LZO
#define CONFIG_LZMA
#define CONFIG_BZIP2

/*
 * Command line configuration.
 */
#include <config_cmd_default.h>
#define CONFIG_CMDLINE_EDITING			/* add command line history	*/
#define CONFIG_AUTO_COMPLETE

#define CONFIG_CMD_ELF
#define CONFIG_CMD_NET
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#define CONFIG_CMD_TFTPPUT
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_NFS

/* Other helpful shell-like commands */
#define CONFIG_MD5
#define CONFIG_CMD_MD5SUM

#define CONFIG_SYS_BOOTM_LEN	SZ_32M	/* max gunzip size */
#define CONFIG_BOOTDELAY	0		/* Autoboot after 0 seconds	*/
#define CONFIG_ZERO_BOOTDELAY_CHECK

#define CONFIG_RANDOM_MACADDR

#endif	/* __CONFIG_LS1B_CORE_H */
